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| WIRELESS COMMUNICATIONS DIVISION TQ3631 C2 Control Logic C2 L1 DATA SHEET VDD GND GND 3V PCS Band CDMA LNA IC RF IN LNA gnd RF 50 ohm OUT RF Out Control Logic C3 Features Small size: SOT23-8 Single 3V operation Low-current operation Product Description The TQ3631 is a 3V, RF LNA IC designed specifically for PCS band CDMA applications. It's RF performance meets the requirements of products designed to the IS-95 specifications. The TQ3631 is designed to be used with the TQ5631 (CDMA mixer) which provides a complete CDMA receiver for 1900MHz phones. The LNA incorporates on-chip switches which determine high, low and bypass mode select. When used with the TQ5631 (CDMA RFA/mixer), four gain steps are available for use which provide low current/high IP3 and gain. The RF output port is internally matched to 50 , greatly simplifying the design and minimizing the number of external components. The TQ3631 achieves excellent RF performance with low current consumption, supporting long standby and talk times in portable applications. Coupled with the very small SOT23-8 package, the part is ideally suited for PCS band mobile phones. Electrical Specifications1 Parameter Frequency Gain Noise Figure Input 3rd Order Intercept DC supply Current Min Typ 1960 13.0 1.5 10.0 11.0 Max Units MHz dB dB dBm mA Gain Select High IP3 performance Few external components Applications IS-95 CDMA PCS Mobile Phones Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, Tc=25C, CDMA High Gain state. For additional information and latest specifications, see our website: www.triquint.com 1 TQ3631 Data Sheet Electrical Characteristics Parameter RF Frequency Conditions PCS band Min. 1810 Typ/Nom 1960 Max. 1990 Units MHz CDMA Mode-High Gain Gain Noise Figure Input IP3 Input Return Loss (with external matching) Output Return Loss Supply Current 7.0 10 10 11.0 13.0 12.0 13.0 1.5 10.0 2.2 dB dB dBm dB dB mA CDMA Mode-High Gain-Low Linearity Gain Noise Figure Input IP3 Input Return Loss (with external matching) Output Return Loss Supply Current 2.0 10 10 4.5 5.5 10.0 11.5 1.6 5.0 2.8 dB dB dBm dB dB mA Bypass Mode Gain Noise Figure Input IP3 Input Return Loss (with external matching) Output Return Loss Supply Current Supply Voltage Note 1: Test Conditions: Vdd=2.8V, RF=1960MHz, TC = 25 C, unless otherwise specified. Note 2: Min/Max limits are at +25C case temperature, unless otherwise specified. -2.5 -1.5 2.0 30.0 2.8 dB dB dBm dB dB 10 10 1.0 2.7 2.8 2.0 3.3 mA V Absolute Maximum Ratings Parameter DC Power Supply Power Dissipation Operating Temperature Storage Temperature Signal level on inputs/outputs Voltage to any non supply pin Value 5.0 500 -40 to 85 -60 to 150 +20 +0.3 Units V mW C C dBm V 2 For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Typical Performance Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=25C, RF=1960MHz CDMA High Gain Mode Gain v Freq v Temp 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 1920 13.00 12.00 11.00 Idd (mA) 10.00 9.00 8.00 7.00 6.00 1940 1960 Frequency (MHz) 1980 2000 2.5 CDMA High Gain Mode Idd v Vdd v Temp Gain (dB) -30C +25C +85C -30C +25C +85C 2.7 2.9 Vdd (V) 3.1 3.3 CDMA High Gain Mode IIP3 v Freq v Temp 10.0 9.5 IIP3 (dBm) 9.0 8.5 8.0 7.5 7.0 1920 -30C +25C +85C High Gain/Low Linearity Mode Gain v Freq v Temp 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 1920 Gain (dB) -30C +25C +85C 1940 1960 Frequency (MHz) 1980 2000 1940 1960 Frequency (MHz) 1980 2000 CDMA High Gain Mode Noise Figure v Freq v Temp 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 1920 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 1920 High Gain/Low Linearity Mode IIP3 v Freq v Temp Noise Figure (dB) IIP3 (dBm) -30C +25C +85C -30C +25C +85C 1940 1960 1980 Frequency (MHz) 2000 1940 1960 Frequency (MHz) 1980 2000 For additional information and latest specifications, see our website: www.triquint.com 3 TQ3631 Data Sheet High Gain/Low Linearity Mode Noise Figure v Freq v Temp 2.50 Noise Figure (dB) 2.00 Noise Figure (dB) 1.50 1.00 0.50 0.00 1920 -30C +25C +85C BYPASS Mode Noise Figure v Freq v Temp 3.00 2.50 2.00 1.50 1.00 0.50 2000 -30C +25C +85C 1940 1960 1980 Frequency (MHz) 0.00 1920 1940 1960 Frequency (MHz) BYPASS Mode IIP3 v Freq v Temp 1980 2000 High Gain/Low Linearity Mode Idd v Vdd v Temp 5.50 5.00 4.00 3.50 3.00 2.50 2.5 2.7 2.9 Vdd (V) 3.1 3.3 -30C +25C +85C IIP3 (dBm) Idd (mA) 4.50 35.0 34.0 33.0 32.0 31.0 30.0 29.0 28.0 27.0 26.0 25.0 1920 -30C +25C +85C 1940 1960 Frequency (MHz) 1980 2000 BYPASS Mode Gain v Freq v Temp 0.0 -0.5 Gain (dB) -1.0 Idd (mA) -1.5 -2.0 -2.5 -3.0 1920 -30C +25C +85C BYPASS Mode Idd v Vdd v Temp 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 2000 0.00 2.5 2.7 2.9 Vdd (V) 3.1 3.3 -30C +25C +85C 1940 1960 1980 Frequency (MHz) 4 For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Application/Test Circuit Vdd R1 Control Logic C2 Vdd C7 GND (paddle) GND L1 LNA input C8 Lbrd LNA GND RF in RF out C3 LNA output Control Logic Bill of Material for TQ3631 LNA Application/Test Circuit Component Receiver IC Capacitor Capacitor Resistor Inductor Inductor Reference Designator U1 C7 C8 R1 L1 Lbrd Part Number TQ3631 2.7pF 1.5pF 3.3 3.9nH See application note Value Size SOT23-8 0402 0402 0402 0402 Panasonic Manufacturer TriQuint Semiconductor For additional information and latest specifications, see our website: www.triquint.com 5 TQ3631 Data Sheet TQ3631 Product Description The TQ3631 LNA uses a cascode low noise amplifier along with signal path switching. A bias control circuit sets the quiescent current for each mode and ensures peak performance over process and temperature, see Figure 1. In the application, CMOS level signals are applied to pins 1 and 5 and are decoded by an internal logic circuit, this sets the device to the desired mode. See Table 1 for truth table. In the high gain mode, switches S1, S2, and S5 are closed, with switches S3 and S4 open. In the bypass mode, switches S1, S2, and S5 are open, with switches S3 and S4 closed. Six internal switches ensures there are no parasitic feedback paths for the RF signal. In the AMPS mode, control logic switches the LNA into a low current bias condition. Only three external components are. The chip uses an external cap and inductor for the input match to pin 3. The output is internally matched to 50 ohms at pin 6. A Vdd bypass cap is required close to pin 8. External degeneration of the cascode is required between pin 4 and ground. However, a small amount of PC board trace can be used as the inductor. Alternatively, if an extra component can be tolerated, a small value chip inductor could be used. See Figure 2. VDD Operation MODE High Gain C2 0 1 High Gain Low linearity Bypass 1 1 -2(dB) 0 C3 0 0 1 11(dB) Typical Gain 13(dB) Table 1 LNA States and Control Bits LNA Input Network Design Input network design for most LNA's is a straightforward compromise between noise figure and gain. The TQ3631 is no exception, even though it has 3 different modes. The device was designed so that one only needs to optimize the input match in the high gain mode. As long as the proper grounding and source inductance are used, the other two modes will perform well with the same match. It is probably wise to synthesize the matching network component values for some intermediate range of Gamma values, and then by experimentation, find the one which provides the best compromise between noise figure and gain. The quality of the chip ground will have some effect on the match, which is why some experimentation will likely be needed. The input match will affect the output match to some degree, so S22 should be monitored. The values used on our evaluation board may be used as a starting point. Control Logic C2 VDD R1 8 1 Bias and Switch Control Logic C7 2 GND 7 GND LNA IN L1 S6 3 S1 6 S2 LNA OUT Noise Parameter Analysis A noise parameter analysis is shown on the next page for the high gain mode. A "nominal" device was mounted directly on an evaluation board with semi-rigid probes attached to the device input and output pins. A value of Lbrd was chosen so that 13.0dB of gain was attained at conjugate match. The tuner was removed and noise data was taken. RFIN RF OUT C8 4 Lbrd DC GND S3 S5 S4 5 Control Logic C3 Figure 1 TQ3631 Simplified Schematic 6 For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Gamma Opt analysis for TQ3631 High Gain Mode Freq. (MHz) 1800 1960 2040 Opt 0.453 0.459 0.437 Angle 95.8 109.4 116.4 Fmin (dB) 1.476 1.178 1.287 R noise Figure 2 Showing Lbrd and Grounding on Evaluation Board 14.2 9.58 8.17 Selection of the Vdd Bypass Cap for Optimum Performance The Vdd bypass capacitor has the largest effect on the LNA output match, and is required for proper operation. Because the input match affects the output match to some degree as well, the process of picking the bypass cap value involves some iteration. First, an input match is selected which gives adequate gain and noise figure. Then the bypass capacitor is varied to give the best output match. The demo board achieves 11-12dB of return loss which is adequate for connection directly to the input of a SAW filter. Gain Control via Pin 4 Inductance The source connection of the LNA cascode is brought out separately through pin 4. That allows the designer to make some range of gain adjustment. The total amount of inductance present at the source of the cascode is equal to the bond wire plus package plus external inductance. One should generally use an external inductance such that gain in the high gain CDMA mode = 13.0dB. Although it is possible to increase the gain of the TQ3631 by using little or no degeneration, input intercept will be degraded. Figure 2 shows how a spiral PC board trace can be used as the external inductance. It is suggested that such a circuit be used for the initial design prototype. Then the optimum inductance can be found by simply solder bridging across the inductor. The final PC board design can then include the proper shorted version of the inductor. Grounding An optimal ground for the device is important in order to achieve datasheet specified performance. Symptoms of a poor ground include reduced gain and the inability to achieve <2:1 VSWR at the output when the input is matched. It is recommended to use multiple vias to a mid ground plane layer. The vias at pins 2 and 7 to this layer should be as close to the lead pads as possible Additionally, the ground return on the Vdd bypass cap should provide minimal inductance back to chip pins 2 and 7. TQ3631 S-Parameters Following are S-Parameter graphs for the high gain and high mode. Data was taken on a single "nominal" device at 2.8v Vdd. The reference planes were set at the end of the package pins. For additional information and latest specifications, see our website: www.triquint.com 7 TQ3631 Data Sheet TQ3631 High Gain Mode S-Parameters S11 TQ3631 High Gain Mode S-Parameters S12 TQ3631 High Gain Mode S-Parameters S21 TQ3631 High Gain Mode S-Parameters S22 8 For additional information and latest specifications, see our website: www.triquint.com TQ3631 Data Sheet Package Pinout C2 Control Logic C2 L1 VDD GND GND RF IN RF 50 ohm OUT RF Out Control Logic GND C3 Pin Descriptions Pin Name C2 GND RF IN DC GND C3 RF OUT GND Vdd Pin # 1 2 3 4 5 6 7 8 Description and Usage Control logic 2 Ground, paddle RF input, off-chip matching required Source of input FET Control logic 3 RF output, no matching required Ground LNA Vdd, typical 2.8V, C7 capacitor required For additional information and latest specifications, see our website: www.triquint.com 9 TQ3631 Data Sheet Package Type: SOT23-8 Plastic Package Note 1 PIN 1 FUSED LEAD b A c E E1 Note 2 DIE e DESIGNATION A A1 b c D e E E1 L Theta A1 L METRIC 1.20 +/-.25 mm .100 +/-.05 mm .365 mm TYP .127 mm TYP 2.90 +/-.10 mm .65 mm TYP 2.80 +/-.20 mm 1.60 +/-.10 mm .45 +/-.10 mm 1.5 +/-1.5 DEG ENGLISH 0.05 +/-.250 in .004 +/-.002 in .014 in .005 in .114 +/-.004 in .026 in .110 +/-.008 in .063 +/-.004 in .018 +/-.004 in 1.5 +/-1.5 DEG NOTE 3 3 3 3 1,3 3 3 2,3 3 DESCRIPTION OVERALL HEIGHT STANDOFF LEAD WIDTH LEAD THICKNESS PACKAGE LENGTH LEAD PITCH LEAD TIP SPAN PACKAGE WIDTH FOOT LENGTH FOOT ANGLE Notes 1. The package length dimension includes allowance for mold mismatch and flashing. 2. The package width dimension includes allowance for mold mismatch and flashing. 3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error. Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: info_wireless@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: info_wireless@tqs.com The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision A, March, 2000 10 For additional information and latest specifications, see our website: www.triquint.com |
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